Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias

In the race against Moores Law, integrated chips (ICs) with multiple dies stacked over one another and connected by ThroughSilicon Vias (TSVs), called 3D TSV-Stacked ICs (SICs) have attracted a fair amount of research [1]–[5]. Due to imperfections in IC manufacturing, each individual chip must be tested. Testing each IC, increases cost, which is highly related to the testing time spent on each IC. Test scheduling approaches, aiming at minimizing testing times, for non-stacked ICs have been discussed in [6]– [8]. Although no work has yet been visible for scheduling tests under power constraints for 3D TSV-SICs. Applying traditional test scheduling methods used for non-stacked chip testing, where the same schedule is applied both at wafer sort and package test, to 3D TSV-SICs, leads to unnecessarily high TAT. This is because in case of 3D TSV-SICs, the package test involves testing of all the chips in the stack together. Therefore, tests scheduled for individual chips during wafer sort using [6], [7] do not perform well during package test. A key challenge in 3D TSV-SIC testing is to reduce TAT by co-optimizing wafer sort and the package test. In our work, we consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure, based on [9], [10] and shown in Fig. 1, and we propose a test scheduling approach to reduce TAT while considering resource conflicts. Fig. 1 illustrates the scan chains that start from a JTAG TAP, proceeds through one or more cores and returns back to the JTAG TAP. It should be noted that, only one scan chain can be accessed at a time. Thus, if tests for more than one core of a chip are to run concurrently, in a session, these cores are connected in series on the JTAG interface, forming a single scan chain. This enforces the concept of sessions as introduced in [6]–[8]. For a single chip, only cores that are in the same scan chain can be tested concurrently. Furthermore, if two cores are to be tested in sequence, in different sessions, they cannot be connected in the same scan chain. On the other hand, a session of tests from a chip can be performed concurrently with a session of tests from another chip by selecting the scan chains in the TAPs of to the two chips. For any core, say Core3 in Fig. 1, the test time (T3) required can be calculated as a function of the length of the scan chain of Core3 (l3) and the number of patterns required (p3):